The CXL (Compute Express Link) technical specification was initiated by Intel in March 2019, with a consortium of industry players joining. This high-speed interface standard aims to address communication latency and insufficient transmission bandwidth between CPUs and accelerators such as GPUs or FPGAs, thereby addressing the increasingly complex computing demands, particularly those driven by the growing development of artificial intelligence (AI) applications.
What is CXL?
In traditional computing architectures, communication between the CPU and GPU occurs via PCIe channels and the PCIe protocol. While the PCI-SIG has consistently advanced PCIe specifications, it clearly cannot keep pace with today's ever-larger data processing demands. Consequently, the CXL specification was developed to address communication latency and insufficient transmission bandwidth between CPUs, GPUs, and other computing components.
Even though NVIDIA has already proposed its NVLink technology, it only applies to communication between NVIDIA GPUs. CXL technology, on the other hand, can support more computing components and can also form a larger market ecosystem, thereby promoting the development of more complex computing applications.
The CXL technical specification is built on the existing PCIe 5.0 and 6.0 specifications. CXL 1.0, 1.1, 2.0, and the current 3.0 versions have been proposed. Versions 1.0 and 1.1 allow the CPU to directly connect to other computing components, but only a one-to-one connection can be achieved at a time. It was not until version 2.0 that many-to-many connections were achieved, thereby increasing computing configuration flexibility. At the same time, memory usage blocks can be dynamically allocated to increase computing flexibility. In addition, data encryption mechanisms are added to provide more secure computing performance.
The CXL 3.0 version currently under development provides multi-layer switching connections and incorporates non-tree switching connection architectures such as mesh or ring. This allows the CPU to communicate more flexibly with more computing elements and improves multi-access capabilities, thereby achieving more complex and larger-scale computing element connections.
相比1.0、1.1與2.0版本是以PCIe 5.0通道建立連結，最高可在單向傳輸實現最高每秒63GB的資料傳輸頻寬，或是在雙向時實現最高每秒126GB的資料傳輸頻寬，目前推進的3.0版本則改為PCIe 6.0通道規格，資料傳輸頻寬約比先前的版本提升一倍。
CXL technology promotes high-speed transmission of computing data using open standard architecture
CXL technology itself adopts an open standard architecture design, and its ecosystem growth is jointly promoted by industry players such as Intel, Samsung, and VMware. It can be used in various processors, accelerators, memory buffer blocks, and even various I/O connection designs to achieve high-speed transmission and low-latency data communication, allowing current memory capacity and transmission bandwidth to break through existing specification bottlenecks and drive greater computing performance.
For example, Intel, one of the main drivers of CXL technology, has already adopted the CXL design in its fourth-generation Xeon Scalable processor series, code-named Sapphire Rapids. AMD has also incorporated CXL technology into its fourth-generation EPYC processor, code-named "Genoa." Memory giants such as Samsung are also actively developing DRAM memory modules that support CXL technology. Furthermore, memory module, CXL controller IP, and server ODM/OEM companies have also made progress, indicating that the relevant hardware and software ecosystem will take shape and enter practical application by 2025.
Samsung's CMM-D (CXL Memory Module – DRAM) module, created by combining CXL technology with its DRAM memory design, dynamically scales memory capacity based on computing demands, meeting the needs of data-intensive workloads while also allowing for future expansion of memory capacity as computing power demands increase. Samsung's 2.0GB DRAM module, designed to meet the CXL 128 specification and utilize the PCIe 5.0 interface, significantly increases memory capacity and bandwidth to meet the needs of AI and high-performance computing applications.
To accelerate the commercialization of next-generation memory solutions, Samsung is actively expanding the CXL technology ecosystem, collaborating with companies such as Intel, Montage Technology, Supermicro, QCT, MSI, GIGABYTE, and H3 Platform.
For example, at the 2024 Red Hat Summit event, Samsung and Red HatPromote open source technology and standardization cooperation, and verify the feasibility of CXL memory technology in real user scenarios.
Industry and Market Outlook
The primary goal of CXL technology is to address the need for low-latency, high-bandwidth connections between computing components such as CPUs, GPUs, and even FPGAs and accelerators, and memory. It is being initially applied to data centers, AI training, and high-performance computing (HPC). For example, cloud service providers such as AWS, Azure, and Google Cloud are leveraging the CXL architecture to create dynamic memory pools, thereby improving the efficiency of resource allocation and utilization in cloud computing environments. It can also flexibly deploy memory capacity and overall data transmission bandwidth to meet the current needs of AI training and inference applications.
As the demand for artificial intelligence, high-performance computing, and other technologies continues to increase, the demand for memory resource applications will also increase accordingly, which will drive CXL technology into more applications.
In the semiconductor sector, processor manufacturers such as Intel and AMD are also utilizing CXL technology, adapting their processors to the CXL architecture's computing model and improving data processing efficiency through increased capacity and higher transmission bandwidth. Furthermore, companies such as Astera Labs, Montage, and Rambus are accelerating the release of new switch and memory expansion solutions, driving further growth in computing scale.
Therefore, we anticipate seeing CXL technology enhance memory deployment flexibility, reduce latency and data transmission bandwidth issues between computing components like CPUs and GPUs, and accelerate the growth of advanced technologies like artificial intelligence. CXL technology will also be extended to modular edge servers, enabling flexible scaling of computing resources through a distributed architecture.
At the same time, the CXL Alliance will also integrate the resources of standards organizations such as PCI-SIG, which develops the PCIe specification, and the Open Compute Project (OCP), to accelerate the update of CXL technology versions and promote the coordinated optimization of software and hardware.
However, the current application cost and deployment complexity of CXL technology are relatively high, and some technologies are not yet mature. In addition, operating systems, drivers and applications also need to be adjusted and optimized for the CXL memory architecture, so application development still faces some resistance.
However, many members of the CCIX (Cache Coherent Interface for Accelerators) technology, initially proposed to improve accelerators' access to memory resources, have gradually transitioned to the CXL specification. Furthermore, the UCIe specification, promoted by Intel, AMD, Qualcomm, Google, and others, is also compatible with CXL. This is beneficial for the future development of CXL technology, and it is likely to become an essential technology for data centers and high-performance computing within the next 3-5 years.
