A joint venture between Intel, AMD, Microsoft, Meta, Google, Qualcomm, Samsung, TSMC, ASE, and other companiesUCIe Industry Alliance, announced earlierNew UCIe 3.0 versionThe open chip interconnect standard specification increases the transmission bandwidth speed from the previous 32GT/s to 48GT/s and 64GT/s, further meeting the high-speed and low-latency data transmission requirements of the next-generation high-performance chiplet architecture for AI, HPC, etc.
Compared with the proposal in August last yearUCIe Version 2.0 SpecificationIn addition to improving bandwidth performance, UCIe 3.0 maintains backward compatibility and introduces multiple architecture and function enhancement designs.
This includes an enhanced mechanism that supports on-the-fly recalibration, enabling energy-efficient connection adjustments without reinitialization and improving overall system efficiency. The newly added edge channel extends to 100mm, enabling a wider range of system-in-package (SiP) topology designs.
In terms of transmission technology, UCIe 3.0 enhances data interoperability between chiplets and components such as SoCs and DSPs through continuous transmission protocol mapping and Raw mode support. It also enables early firmware download capabilities through the MTP (Multi-Tile Programming) standardized process, effectively simplifying the development phase.
For time-sensitive computing applications, UCIe 3.0 introduces a priority sideband packet mechanism to ensure that critical system events are delivered instantly and with low latency. At the same time, through rapid throttling and emergency shutdown designs, it supports real-time system-level notifications through open-drain (OD) I/O, further ensuring stability and security.
Since its establishment in 2022, the UCIe Industry Alliance has emphasized the creation of an open, standardized and flexible chip interconnection architecture based on general technologies such as PCIe and CXL, which will help semiconductor design evolve from traditional single chips to modular and chip-based technology.
The release of the UCIe 3.0 design specification is expected to further promote innovation and implementation of high-performance computing, artificial intelligence, and advanced packaging technologies in the chip design industry.
