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Home Market dynamics

CXL 3.0 design specifications released, enhancing communication between CPUs and other accelerators and increasing data transfer rates

Author: Mash Yang
2022-08-03
in Market dynamics, Processor, observe
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Incorporated into the OpenCAPI standardLater, the CXL (Compute Express Link) Alliance announcedVersion 3.0 Design Specifications, mainly expanding the architecture design and data transmission management capabilities, and enhancing the communication and linkage efficiency between the CPU and other accelerators.

CXL 3.0 design specifications released, enhancing communication between CPUs and other accelerators and increasing data transfer rates

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Siamak Tavallaei, president of the CXL Consortium, said CXL technology will continue to help promote the heterogeneous and scalable combination design required by modern data centers, enabling applications such as artificial intelligence and machine learning to be completed through more intensive workloads by improving computing performance.

The CXL 3.0 design specification announced this time adds fabric management capabilities, including support for multi-Fabric connections, enhanced management and group classification, improved memory sharing, pooling, and enhanced consistency, and the addition of P2P peer-to-peer communication and software capabilities.

In addition, the CXL 3.0 design specification increases the data transmission rate to 64 GT/s, which will be more than twice the current CXL 2.0 specification, while being backward compatible with the CXL 2, CXL 2.0 and CXL 1.1 design specifications.

CXL 3.0 design specifications released, enhancing communication between CPUs and other accelerators and increasing data transfer rates

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Tags: Compute Express LinkCXLCXL3.0
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Mash Yang

Mash Yang

Founder and editor of mashdigi.com, and student of technology journalism.

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