Tag: RISC-V

Amid the global wave of semiconductor self-sufficiency, India has finally delivered its first achievement. The Indian government officially announced the successful development of the country's first domestically developed 64-bit dual-core microprocessor (MPU), codenamed "DHRUV64". This chip adopts the open-source RISC-V instruction set architecture, symbolizing a crucial step forward for India in establishing its indigenous semiconductor ecosystem. While its specifications may not be top-tier by 2025 semiconductor technology standards, the 28nm process and focus on embedded systems and the Internet of Things (IoT) represent a significant milestone for India's emerging semiconductor industry. According to official data, DHRUV64 possesses the following characteristics: • Architecture: Based on the RISC-V open-source instruction set, meaning India does not need to pay expensive licensing fees to Arm or Intel. • Core Configuration: 64-bit dual-core design with a clock speed of 1.0 GHz. • Technical Details: Supports out-of-order (OoO) and superscalar computing technologies, featuring approximately 30 million logic gates. • Manufacturing Process: Utilizes a 28nm process. Judging from the official chip layout diagram, this processor is clearly not designed for smartphones or high-performance computing, but rather leans towards industrial control, Internet of Things (IoT) devices, or basic consumer electronics. Next Steps: The Dhanush series takes over. The Indian Ministry of Electronics and Communications Technology (MeitY) is not stopping there, emphasizing that DHRUV64 is just the beginning, and will subsequently develop the next-generation processor series codenamed "Dhanush" and "Dhanush+". Although specific specifications have not yet been announced, it is expected to move towards more advanced processes (such as 12nm or higher) and higher core counts to further expand the application ecosystem of Indian-made MPUs. Analysis: RISC-V becomes the preferred choice for national strategy...

To further solidify its technological leadership in computing, Qualcomm recently announced the acquisition of Ventana Micro Systems. This acquisition will strengthen Qualcomm's CPU engineering capabilities by integrating Ventana's expertise in RISC-V instruction set architecture (ISA) development, and demonstrate its commitment to advancing the RISC-V standard and ecosystem. Integrating RISC-V expertise to drive Oryon CPU development, Qualcomm stated that the addition of the Ventana Micro Systems team will complement Qualcomm's existing RISC-V and customized Oryon CPU development efforts. This means that Qualcomm is not only continuing to refine its existing architecture but also attempting to integrate Ventana Micro Systems' experience in high-performance RISC-V design into its technology strategy for its entire product line in the AI ​​era. Durga Malladi, Executive Vice President and General Manager of Qualcomm's Technology Planning, Edge Solutions, and Data Center, stated, "At Qualcomm, we are committed to shaping the future of intelligent computing. We believe that the RISC-V instruction set architecture has the potential to advance CPU technology to the forefront and drive innovation across a wide range of products." He emphasized that the acquisition of Ventana Micro Systems is a key step for Qualcomm in providing industry-leading RISC-V CPU technology. The two companies are joining forces to drive next-generation high-performance computing. Ventana Micro Systems CEO Balaji Baktha stated, "We are delighted to join the Qualcomm team and contribute our expertise in RISC-V to assist in the development of Qualcomm's Oryon CPU technology." He believes this acquisition opens an exciting new chapter, and together they will push the limits of energy efficiency and high performance in next-generation products. Strengthening independent design development and securing more opportunities, this acquisition further highlights Qualcomm's ambition in CPU self-development. In addition to its existing Arm architecture, Qualcomm is actively using acquisitions to deepen its influence and technological foundation in the RISC-V open architecture field. Especially given Qualcomm's recent relationship with Arm affected by the instruction set licensing lawsuit, even though it later won the court ruling and used the new Armv9 instruction set in subsequent processor designs, it highlights Qualcomm's desire to avoid further limitations in instruction set architecture design and its expectation to secure more development opportunities through its RISC-V architecture design strategy.

As the demand for generative AI and edge computing continues to rise, RISC-V technology provider SiFive officially launched its second-generation Intelligence series IP in Santa Clara, USA, bringing five products to target diverse AI applications from deeply embedded edge devices to data centers. This update includes two newly designed X160 Gen 2 and X180 Gen 2 processors, as well as upgraded versions of the X280 Gen 2, X390 Gen 2, and XM Gen 2, comprehensively enhancing scalar and vector processing capabilities and introducing matrix operations to the XM series for the first time, optimized for modern AI workloads. SiFive points out that the X160 and X180 are miniaturized designs for remote computing and IoT applications, providing higher performance in a very small area and low power consumption, allowing edge devices such as smart cars, robots, and industrial automation to incorporate AI functionality at a lower cost. The X280, X390, and the XM with a matrix engine target high-end AI computing scenarios, spanning from narrow vector to large-scale matrix operations, providing customers with flexible configuration options. Patrick Little, CEO of SiFive, stated that AI is driving RISC-V into its next era of development. Two leading US semiconductor companies have already adopted the X100 series solution. He also emphasized that the second-generation Intelligence IP not only improves performance but also provides greater configurability, helping customers shorten design cycles and time-to-market. Deloitte predicts that AI workloads will continue to grow by more than 20% across various computing environments, with edge AI computing growing by nearly 80%. Pat Moorhead, founder of Moor Insights and Strategy, pointed out that SiFive has precisely targeted the edge AI market, which requires high efficiency and flexibility. Its new generation of products addresses real customer pain points and provides reliable solutions with a unique performance-power balance strategy. SiFive emphasizes the advantages of its vector processing technology, which can process multiple data simultaneously, reducing instruction overhead and power consumption. Compared to traditional pure scalar CPUs, vector processors can run AI models faster in a smaller area, making them an ideal choice for edge applications. Furthermore, all X-series IPs can serve as Accelerator Control Units (ACUs), using dedicated interfaces (SSCI, VCIX) to control external accelerators, helping customers simplify software stacking and focus on system-level innovation. Five products are currently available for licensing, with the first application chip expected in the second quarter of 2026.

Raja Koduri, a legendary architect who previously worked at AMD and Apple and successfully drove the development of numerous display applications, left Intel in March 2023. He recently announced the founding of a new startup called Oxmiq Labs on his personal "X" page. Oxmiq Labs will challenge NVIDIA's CUDA computing platform ecosystem with a RISC-V architecture-based GPU and software design solutions. ▲ Raja Koduri's startup, Oxmiq Labs, will focus on GPU hardware and software technology development and operate through a licensing model. Its biggest highlight is its software layer solution called OXPython, which allows developers to run CUDA workloads based on the Python programming language on non-NVIDIA GPU hardware environments without modifying any code, thereby improving the openness and application flexibility of the computing platform. Based on the RISC-V architecture, Oxmiq Labs' OxCore GPU design utilizes the RISC-V instruction set architecture, combining scalar, vector, and tensor operation units to support near-memory and embedded memory operations. Coupled with the OxQuilt chiplet SoC architecture tool, customers can quickly assemble multi-core computing modules, memory modules, and interconnect modules according to their needs, flexibly creating customized chip solutions for different scenarios, from edge AI inference to large-scale AI training. ▲Oxmiq Labs' hardware core, OxCore, adopts the RISC-V instruction set architecture, combining scalar, vector, and tensor operation units to support near memory and embedded memory operations. Emphasizing that software is key, Oxmiq Labs places more emphasis on the value of software stacking compared to hardware. Its core platform, OXCapsule, abstracts the underlying hardware differences with a unified runtime and scheduling layer, encapsulating application services into independently operable "heterogeneous containers." This allows developers to deploy and execute tasks on different CPUs, GPUs, or AI accelerators without having to deal with complex configurations. ▲The core platform OXCapsule abstracts the underlying hardware differences through a unified runtime and scheduling layer, encapsulating application services into independently operable "heterogeneous containers." This allows developers to deploy and execute tasks on different CPUs, GPUs, or AI accelerators without having to deal with complex configurations. Among them, the OXPython software layer solution can translate Python applications based on the CUDA computing platform into the Oxmiq execution environment. The first wave of supported platforms will be the Wormhole AI processor and Blackhole AI accelerator from Tenstorrent, a chip startup invested in by Amazon founder Jeff Bezos and Samsung. Tenstorrent CEO Jim Keller stated that Oxmiq Labs' technology will significantly improve the portability of the developer ecosystem, aligning with the development trend of open AI hardware and software computing resource stacking. While Raja Koduri has led several graphics card architectures in the past, Oxmiq Labs has not developed consumer-grade GPUs, nor does it include features such as ray tracing or image output. Its business model is primarily IP licensing, meaning licensees will need to complete the necessary modules themselves to build a full GPU. Furthermore, Oxmiq...

At the recent RISC-V Summit China, Frans Sijsterman, NVIDIA's Vice President of Hardware Engineering, announced that CUDA will support RISC-V processors. This means that this key technology for deep learning and GPU acceleration applications will be able to run in a more diverse processor ecosystem, further expanding the possibilities of heterogeneous computing. Previously, CUDA was primarily used on x86 or Arm architecture processor platforms. This announcement of support for RISC-V processors not only echoes NVIDIA's open strategy regarding CPU pairings in its GPU products but also highlights NVIDIA's emphasis on the Chinese market. Especially given the increasingly tense US-China relations and the rising cost of Arm architecture licensing, many Chinese companies are beginning to replace their previous x86 or Arm architecture processor designs with open-source RISC-V processors. Expanding support for RISC-V processors will also allow NVIDIA to embrace more development opportunities. Exciting news from #RISCVSummitChina, as Frans Sijsterman from NVIDIA announces CUDA is coming to RISC-V! This port will enable a RISC-V CPU to be the...

GlobalFoundries (GF), a semiconductor foundry, announced on July 8th (US Pacific Time) that it will acquire processor technology asset provider MIPS. This acquisition will strengthen GF's capabilities in RISC-V architecture processor cores, software tools, and other technologies, expanding its competitive advantage in markets such as AI, autonomous driving, industrial automation, data centers, and edge intelligence. The transaction is expected to close in the second half of 2025, pending regulatory approval. Following the acquisition, MIPS will operate as an independent division within GlobalFoundries. GlobalFoundries stated that this acquisition will allow it to further combine its process technology advantages with MIPS's scalable processor technology assets to provide more flexible customized solutions, helping customers create high-performance, low-power, and future-proof chip products. GlobalFoundries COO Niels Anderskouv further stated, "MIPS possesses strong computing technology assets for developing high-performance mission-critical applications, perfectly aligning with the increasingly diverse market demands for AI platforms. This acquisition will allow us to expand our RISC-V-based open platform product portfolio in applications such as autonomous vehicles, industrial applications, and data centers." In recent years, MIPS has continuously promoted processor technology based on the open architecture RISC-V and launched the Atlas series product portfolio, covering real-time processing, application processors, and AI edge computing cores. Through the Atlas Explorer virtual platform, it assists chip design teams in optimizing processor performance, power consumption, and area at an early stage, enhancing overall development efficiency. MIPS CEO Sameer Wasson stated that joining GlobalFoundries will allow them to leverage GlobalFoundries' global manufacturing, cybersecurity, and long-term supply capabilities to accelerate the development of "Physical AI" applications such as autonomous vehicles and industrial robots, opening a new chapter in the company's development. In the future, MIPS will continue to operate as an independent business unit, serving customers in the global autonomous driving, industrial control, and embedded markets. GlobalFoundries has been actively expanding its presence in the AI ​​chip foundry market in recent years. Besides strengthening its FinFET and FD-SOI process technologies, it is also committed to open architecture platforms, physical technology assets, and chip security. This acquisition of MIPS will not only expand its processor technology asset portfolio but also enhance GlobalFoundries' ability to provide customers with complete "design-to-manufacturing" solutions. MIPS has previously undergone several resales and even shifted from its original Arm architecture to the RISC-V architecture. Founded in 1981 by John Hennessy, president of Stanford University and current chairman of Alphabet, MIPS, also based on a reduced instruction set architecture, was once a direct competitor to Arm. However, compared to the continued expansion of the Arm architecture, MIPS's less open architecture licensing model resulted in numerous limitations in applications, gradually causing it to lose its competitive edge in the market. In November 2012, it was acquired by Imagination Technologies. However, Imagination Technologies subsequently failed in the market and sold MIPS to Wave Computing. Although they open-sourced the MIPS architecture in hopes of attracting more market users, the market had almost entirely shifted to the Arm architecture design and development model, further limiting the development space for the MIPS architecture. Therefore, they fully transitioned to the RISC-V camp, which also uses an open-source architecture, and built their subsequent processor products based on the RISC-V architecture, focusing on security and high performance, targeting application scenarios such as autonomous driving, industrial control, and edge AI. As AI technology continues to extend to the edge and physical devices, the RISC-V architecture has rapidly risen due to its open and modular characteristics. GlobalFoundries' acquisition of MIPS is expected to further promote the application of the RISC-V architecture in high-performance and low-power computing, accelerate the evolution of the global AI ecosystem, and combine the manufacturing, design, and ecosystem integration advantages of both parties to provide more efficient, flexible, and secure AI solutions for the automotive, industrial, data center, and edge computing markets, strengthening their competitiveness in the next generation of intelligent computing landscape.

RISC-V Taipei Day officially kicked off today (May 20th) on the first day of Computex 2025. The newly established RISC-V Taiwan Pavilion brings together 18 ecosystem partners from home and abroad, including Andes Technology and Tensorrent, to showcase their achievements in various applications such as AI chips, NPUs, and chip security. Through hands-on demonstrations and expert tours, the pavilion presents the development potential of the RISC-V architecture in the fields of high-performance computing and edge intelligence. The main pavilion brought together 18 partners to showcase a variety of customized AI chips and security solutions. This year's exhibitors spanned IC design, AI development, IP licensing, and system integration, including Andes Technology, Tensorrent, Skymizer, Zhicheng Electronics, RIVOS, RISE Project, DeepComputing, Nuclei Technology, Semidynamics, Alibaba DAMO Academy, National Chiao Tung University Artificial Intelligence System Testing Center, and the Southern Taiwan Chip Design Promotion Base (Zhongshan Industrial Development), Ministry of Economic Affairs' Industrial Development Agency. They jointly exhibited technological achievements covering RISC-V IP, AI chips, NPU, LLM acceleration IP, 3DIC WoW packaging technology, the myPDA digital avatar platform, and the integrated LLM development platform myLLM Studio. Furthermore, RISC-V Taipei Day received support from Powerchip Technology, QuantumCTek, MediaTek, Realtek, Qualcomm, and the ITRI Opto-Electronics Laboratory, further strengthening Taiwan's influence in the RISC-V ecosystem. The RISC-V open-source architecture accelerates technological democratization, working hand-in-hand with global industries towards an innovative future. The Taiwan RISC-V Alliance emphasizes that the RISC-V architecture boasts advantages such as open source, modularity, and high flexibility, enabling developers to quickly create competitive AI chip solutions, reduce security vulnerability risks, and increase development transparency. It also possesses the potential to accelerate inference performance and enhance edge privacy protection. Through its concentrated demonstration and cross-industry forum at Computex 2025, the Taiwan RISC-V Alliance hopes to continue promoting exchanges between industry, government, and academia, jointly driving the next wave of technological revolution in AI and secure computing. The RISC-V Taipei Day forum will be held on May 21st, exploring new trends in AI and security applications. To promote industry understanding of RISC-V architecture technology and application prospects, the Taiwan RISC-V Alliance will hold the "RISC-V Taipei Day Forum: Pioneering AI with..." on May 21st in Room 505, Hall 1, Nangang Exhibition Center.

Arm recently demanded a response from Qualcomm, threatening to revoke its instruction set license within 60 days if Qualcomm refused. Qualcomm responded by stating that its architecture licensing agreement already covered a wide range of rights, even alleging that Arm intended to increase licensing fees. Unable to reach an agreement, the two companies are scheduled to meet in court on December 16th (US time), with Arm CEO Rene Haas and Qualcomm CEO Cristiano Amon testifying. The lawsuit stems from Qualcomm's 2021 acquisition of NUVIA, a chip design company headquartered in Santa Clara, California. Since NUVIA already held an Arm architecture license, and Qualcomm also held licenses from Arm, it argued that it should inherit NUVIA's existing licenses upon acquisition. However, Arm believes that Qualcomm must reapply for a license from Arm to effectively inherit and use NUVIA's existing architecture license. Qualcomm maintains that its existing licenses are sufficient to cover the technology used in its current designs. Therefore, unable to reach a consensus, Arm filed a lawsuit against Qualcomm. Arm emphasized that its lawsuit against Qualcomm was to protect its intellectual property rights. The market believes that Arm's significant action in suing one of its major customers, Qualcomm, is likely aimed at preventing other large customers from following suit by acquiring other chipmakers to expand technology licensing, thus preventing Arm from profiting through re-licensing. Therefore, Arm is willing to resort to legal action to force Qualcomm to re-license. However, given Qualcomm's past experience with licensing agreements with companies like Apple and Foxconn, it is not unfamiliar with court proceedings and is expected to have prepared corresponding measures to confront Arm in court. Therefore, the outcome of the Arm-Qualcomm lawsuit has become a key focus for many in the market. If the court rules against Arm, it means more companies will follow Qualcomm's approach and indirectly acquire Arm technology licenses through acquisitions. If Qualcomm loses, it could lead to price increases for Snapdragon processors, resulting in higher prices for related applications, and might even force Qualcomm to switch to the RISC-V architecture, potentially causing Arm to lose a major customer.

Regarding Qualcomm's announcement that it will expand the application of its proprietary Oryon CPU architecture in its products, and its recent announcement of a collaboration with Google to create a Wear OS-compatible, RISC-V-based smart wearable solution, Dino Bekis, Qualcomm's Vice President and General Manager of Wearable and Mixed-Signal Solutions, explained in an interview that the primary consideration is the actual application requirements. Wearable devices, in particular, place a strong emphasis on battery life and extended usage, which may lead to different design approaches. ▲Wearable devices prioritize battery life and extended usage; Qualcomm may have different design approaches for such devices. The RISC-V architecture is not the only development direction for wearable devices; Qualcomm hopes to gain more opportunities through this approach. While Qualcomm has indeed stated its plan to widely apply Oryon CPU designs in its products, including wearable device applications, the emphasis on extended battery life and a more stable user experience in these applications has led to the recent announcement of a collaboration with Google to create a computing platform more suitable for wearable devices based on the RISC-V architecture. However, this decision doesn't mean Qualcomm won't consider using Oryon CPUs in wearable devices. It primarily depends on the final product design considerations, such as applications in virtual reality headsets requiring higher computing performance, or smartwatches with more features, even capable of replacing smartphones. ▲Dino Bekis, Vice President and General Manager of Wearable and Mixed-Signal Solutions at Qualcomm. Given the current tensions between Qualcomm and Arm, Qualcomm's recent moves to develop RISC-V architecture applications can be seen as a backup plan besides Arm architecture development. This would allow for additional development space should Arm architecture applications face obstacles, or prevent being limited to Arm-based designs. It could also serve as leverage in renegotiating with Arm. Furthermore, adopting RISC-V architecture in wearable devices, with a relatively smaller impact, can also serve as a testing ground for Qualcomm. If successful in wearable applications, it might be expanded to mobile computing devices and other application scenarios. Even if it ultimately fails, the impact on Qualcomm would be relatively small. However, Qualcomm has not completely abandoned the Arm architecture for building smart wearable application computing platforms. They also stated that their current development strategy will not follow the annual update frequency of mobile computing platforms, but rather release major updates every 2-3 years, coupled with minor design changes during transition periods, and add more new features through software definition. This product development model can meet the needs of most current smart wearable device usage scenarios. While artificial intelligence applications have their significance in wearable devices, current practices do not favor completing all computations on the device itself. Regarding Qualcomm's emphasis on deploying various artificial intelligence applications through its computing platform, and how this will be handled in wearable devices, Dino Bekis responded that such device designs will be based on longer battery life, and will incorporate various sensors to record wearer's body data and interactive usage data. This will allow more useful signals to be transmitted to the cloud for collaborative computation, enabling related applications to monitor the wearer's physical condition more in real time, or to use the data to create better human-computer interaction methods. While current AI technology development tends to place models on the device side, allowing all data to be processed there, Dino Bekis believes that applying automatically generated AI to wearable devices, primarily smartwatches, is not very practical for these devices. It's more suitable for improving data recognition and retrieval, such as making it easier for users to use digital assistant services on the watch, and allowing the watch to more accurately record the user's health status. ▲The future may see a shift towards wearable device experiences focused on computer vision applications. However, deploying AI in wearable devices still has its significance. For example, as smart glasses-type wearable devices become more widespread, and even applications based on computer vision interaction emerge, Qualcomm may consider incorporating more powerful CPU designs and richer automatically generated AI applications into wearable devices. Dino Bekis believes that the future development of wearable devices will focus more on cross-device connectivity and interaction, rather than replacing specific devices. He believes that distributed computing will remain the mainstream model, allowing computing needs to be met across different devices. Therefore, for Qualcomm, wearable device applications remain an important development area.

SiFive announced the new SiFive Performance P870-D datacenter processor to meet customer needs for highly parallel infrastructure workloads, including video streaming, storage, and networking devices. Combined with products in the SiFive Intelligence family, datacenter architects can also build a highly efficient, energy-saving computing subsystem for AI-driven applications. Building upon the previously released P870, the SiFive Performance P870-D supports the open AMBA CHI protocol, giving customers greater flexibility in scaling cluster sizes. This scalability allows customers to maximize performance while minimizing power consumption. Utilizing the standard CHI bus, the SiFive Performance P870-D can scale to 256 cores using industry-standard protocols such as CXL (Compute Express Link) and CHI chip-to-chip (C2C), enabling consistency across high-core-count heterogeneous SoCs and die configurations. Compared to competitors, SiFive offers higher performance per watt for workloads requiring multiple computing tasks to run in parallel. Therefore, the SiFive Performance P870-D offers a competitive advantage in total cost of ownership, while its power efficiency aligns with the industry's growing focus on sustainability. Key features of the SiFive Performance P870-D include: • Providing solutions tailored to computing needs, supporting expansion up to 256 cores • Fully compatible with RVA23 configuration files, enabling system developers to leverage a wide range of operating systems, toolchains, and application software frameworks, thereby shortening time-to-market while reducing project risk and development costs • Support for RISC-V Sv57 extensions, enabling 57-bit virtual address space support...