Tag: NVMe

The UCIe industry consortium, comprised of companies such as Intel, AMD, Microsoft, Meta, Google, Qualcomm, Samsung, TSMC, and ASE, recently announced the new UCIe 3.0 open chip interconnect standard specification. This version increases transmission bandwidth from the previous 32GT/s to 48GT/s and 64GT/s, further addressing the high-speed, low-latency data transmission requirements of next-generation high-performance chiplet architectures such as AI and HPC. Compared to the UCIe 2.0 specification proposed last August, UCIe 3.0 not only improves bandwidth performance but also maintains backward compatibility and incorporates several architectural and functional enhancements. These include an enhanced mechanism supporting runtime recalibration, enabling energy-efficient connection adjustments without reinitialization and improving overall system performance. The newly added edge channel has been extended to 100mm, facilitating more diverse system-in-package (SiP) topology designs. In terms of transmission technology, UCIe 3.0 enhances data interoperability between chips and components such as SoCs and DSPs through continuous transmission protocol mapping and Raw mode support. It also enables early firmware download functionality via the MTP (Multi-Tile Programming) standardized process, effectively simplifying the development phase. For time-sensitive computing applications, UCIe 3.0 introduces a priority sideband packet mechanism to ensure real-time, low-latency transmission of critical system events. Simultaneously, through rapid throttling and emergency shutdown design, it supports real-time system-level notifications via open-drain (OD gate) I/O, further guaranteeing stability and security. Since its establishment in 2022, the UCIe Industry Consortium has emphasized building an open, standardized, and flexible chip interconnect architecture based on general-purpose technologies such as PCIe and CXL, facilitating the evolution of semiconductor design from traditional single-chip to modular and chip-based technologies. The release of the UCIe 3.0 design specification is expected to further promote innovation and implementation in high-performance computing, artificial intelligence, and advanced packaging technologies within the chip design industry.

Sandisk announced its new UltraQLC technology platform and the launch of enterprise-class NVMe SSDs with storage capacities up to 256TB. This product combines BiCS8 QLC CBA NAND, a custom controller, and system-optimized design to achieve not only ultra-high capacity but also improved transmission performance and energy efficiency, targeting the massive data processing demands of the AI ​​era. Sandisk stated that as AI-driven workloads continue to grow, enterprises' needs for the flexibility and scalability of flash storage have increased significantly. The new UltraQLC platform is designed for data-intensive applications, including AI data lakes, data retrieval, and high-speed analytics, maintaining stable and high-speed operating performance while reducing total cost of ownership (TCO). Sandisk's Chief Product Officer, Khurram Ismail, stated, "Entering the next phase of the AI ​​era, flash storage is not only infrastructure but also the core driving force behind high-performance computing and intelligent applications. The UltraQLC platform is the culmination of years of research and development, balancing capacity, performance, and energy efficiency to help customers accelerate the transformation of data into innovative results." Key features of the UltraQLC technology platform include: • Direct Write QLC technology: Power-loss protection from the first data write, eliminating reliance on SLC caching mechanisms. • BiCS8 2Tb QLC bare die: Achieving double the storage density in a small package. • Dynamic power optimization: UltraQLC frequency modulation improves performance by approximately 10% at the same power consumption. • Multi-core controller architecture: Maintaining high throughput and endurance at ultra-large capacities. • Optimized data retention mechanism: Reducing recycling cycles by up to 33%, improving SSD reliability and reducing power consumption. Sandisk stated that this UltraQLC 256TB NVMe SSD will be available alongside the SN670 128TB...

The NVM Express organization has officially released updates to the next-generation NVMe specification, including 11 specification versions such as the NVMe 2.3 basic specification. These updates further enhance data storage performance and management flexibility, meeting the needs of data-intensive applications in AI, cloud, enterprise, and personal use. The updates include the NVMe 2.3 basic specification, multiple updates to command sets (such as five instruction sets: NVM, ZNS, Key Value, Local Memory, and Compute Program), three major transport protocol specifications (PCIe, RDMA, and TCP), and the NVMe-MI management interface 2.1 and NVMe Boot 1.3, reflecting the continuous evolution of NVMe technology in high-performance storage architectures. Amber Huffman, Chair of NVM Express, stated, "The latest NVMe specification strengthens control over data centers and mission-critical environments, further expanding NVMe's role in modern storage architectures. From its inception, NVMe has been designed with sustainable scalability at its core, aiming to support the long-term needs of next-generation high-speed, high-efficiency storage." Among the most anticipated new features are: • Rapid Path Failure Recovery: When communication between the master controller and the NVM subsystem fails, this feature allows the system to automatically switch to other available communication channels, preventing data corruption or duplicate command execution, thus improving system stability and fault tolerance. • Power Limit Config: Allows administrators to set the maximum power consumption of NVMe devices, specifically designed for older equipment or environments with limited power supply, enhancing deployment flexibility and energy management. • Self-reported Drive Power: NVMe...

Micron announced that its consumer-grade 2550 NVMe SSD, featuring a 232-layer NAND design and based on the PCIe Gen4 architecture, is now available to PC OEMs worldwide. It is expected to be used in mainstream laptops and desktops, improving data access efficiency while reducing device power consumption. According to Micron, the consumer-grade 2550 NVMe SSD, in PCMark 10 benchmark tests, shows a 112% improvement in file transfer speeds compared to competing products, approximately 67% faster execution of office productivity applications, 57% faster loading of large games, and a 78% faster execution of content creation applications. It also offers sequential read performance of up to 5GB/s and sequential write performance of up to 4GB/s, representing improvements of 43% and 33% respectively in sequential read and write performance compared to the previous generation. By optimizing the activation and deactivation of automatic power-saving states, employing an advanced process node design in the controller, and utilizing Host Memory Buffer (HMB) technology to remove DRAM and save power, this SSD achieves battery sleep power consumption below 2.5mW, idle power consumption below 150mW, and dynamic power consumption below 5.5W, thereby extending device battery life. The Micron 2550 NVMe SSD is available in three sizes: 22 x 80mm, 22 x 42mm, and 22 x 30mm, with capacities of 256GB, 512GB, and 1TB.

KLEVV, a new memory brand under Hong Kong-based Essencore, announced the launch of three M.2 NVMe SSDs: the CRAS C930, CRAS C910, and CRAS C730, catering to different usage needs. The CRAS C930 and CRAS C910 both come with dedicated aluminum heatsinks, allowing users to customize the installation. The CRAS C930 offers a 1500 TBW lifespan and features a DRAM cache design to reduce heavy workloads. Built with a PCIe Gen 4 x 4 interface and the NVMe 1.4 protocol standard, the 2TB version supports sequential read speeds of up to 7400MB/s and write speeds of up to 6800MB/s, as well as 4K random read and write performance of up to 1000K IOPS. The CRAS C930 is not only suitable for PCs and laptops, but also complies with PlayStation 5 specifications. It can be used with specially designed finned aluminum heatsinks to achieve up to 20% cooling performance. The CRAS C910 also uses an NVMe 1.4 compliant design and employs PCIe Gen 4 x...

During the Tokyo Game Show, Sony's independent storage subsidiary Nextorage demonstrated a high-performance M.2 2280 SSD with a PCIe 5.0 x4 interface, boasting transfer speeds of up to 10 GB/s. ▲ (Image/Excerpt from GDM website) This M.2 SSD can be configured with either active or passive cooling systems. The version showcased at the event featured a passive heatsink with prominent heatsink fins, but the actual design may be adjusted in the final product. According to Nextorage, this M.2 SSD uses a 176-layer NAND design, achieving a transfer speed of up to 10 GB/s. The 2TB version offers sequential read speeds of 10000 MB/s and sequential write speeds of 9500 MB/s, while the 1TB version boasts sequential read and write speeds of 9500 MB/s and 8500 MB/s, respectively. Among its existing products, Nextorage already offers PCIe 4.0 NVMe M.2 SSDs with capacities up to 4TB, with read and write speeds of up to 7300 MB/s and 6900 MB/s respectively, suitable for gaming PCs or PlayStation 5 storage and read needs.

Intel, AMD, Microsoft, Meta, Google, Qualcomm, Samsung, TSMC, and other companies announced the formation of the UCIe Industry Consortium and proposed the UCIe 1.0 design specification, planning to promote the application ecosystem of Chiplet technology. Following the success of interconnect technologies such as PCIe, CXL, and NVMe, Intel, AMD, TSMC, and others plan to popularize Chiplet-based microchip designs, hoping to establish chip interconnects and compatible operation using the UCIe 1.0 specification. This will allow more companies to build new processors according to this standard and to create differentiated designs for different microchips. The UCIe 1.0 specification covers the physical layer of chip-to-chip I/O ports, as well as chip-to-chip interconnect protocols and software stacking designs, leveraging the mature PCI Express (PCIe) and CXL (Compute Express Link) interconnect protocols for faster data transfer efficiency. The first wave of companies joining the UCIe industry alliance includes chip designers, foundries, cloud service providers, and chip design technology companies. After developing the UCIe 1.0 specification, they will continue to move towards the next version of the design, which will define the microchip form factor, management, enhanced security, and related necessary agreements.

With the increasing prevalence of applications such as self-driving cars, smart cities, edge computing, and cloud data centers, Seagate emphasizes that data volume has increased from EB (Exabyte) to ZB (Zettabyte). Its total hard drive shipments have also increased from 120EB in Q3 FY2020 to 159EB in Q1 FY2022. Simultaneously, the average storage capacity per hard drive has continued to increase from 4.1TB to over 5TB, and it has even launched hard drives with a capacity of up to 20TB. In the future, it aims to achieve storage capacities of 60TB or 100TB or more per hard drive through technologies such as HAMR. ▲Seagate will focus more on developing its own branded solutions to explore new storage application possibilities. In addition, Seagate plans to reduce the footprint of hard drive devices, such as by enabling NVMe interfaces, thereby simplifying server size and increasing storage capacity more efficiently within limited space. With the announcement of the Exos AP enterprise data storage system controller powered by AMD EPYC server processors, and the previously announced Lyve Cloud and Lyve Mobile solutions designed for the needs of autonomous vehicles and smart cities, Seagate further stated that it will focus more on developing its own branded solution design products to explore new storage application possibilities. ▲Data volume has increased from ZB (Zettabyte) to EB (Exabyte) scale. Regarding the continued boom in quantum computing, Seagate believes it will provide more suitable storage solutions to meet the demands of such computing. However, it emphasizes that the essence of storage will continue to move towards increasing the storage capacity on a single device and refining access interface design to cope with larger-scale storage needs. In terms of future storage trends, Seagate anticipates that with advancements in quantum mechanics and other computing technologies, encryption techniques based on classical cryptography will become insecure. Therefore, new encryption technologies and new cryptography arising from quantum computing will inevitably develop, possibly within the next few years. Furthermore, with the continuous evolution of computing architectures and the development of decentralization, storage technologies are expected to adapt accordingly. The evolution of Web 3.0 and the metaverse will change storage methods, making distributed storage applications mainstream and increasing storage capacity demands to the petabyte (PB) level. As cloud-native and containerized applications become more widespread, more enterprises will manage services through virtualized storage, making future storage applications more flexible, but also requiring the development of new data management and verification technologies. Given the continued growth in storage capacity, Seagate believes that data security will become even more critical in the future. Therefore, ensuring data encryption, transmission, and handling of storage devices when they are no longer in use will become more stringent. ▲ Continuously increasing single-disk storage capacity through technologies such as HAMR ▲ Lyve Cloud and Lyve Mobile solutions designed for the needs of autonomous vehicles and smart cities ▲ Exos AP enterprise data storage system controller using AMD EPYC server processors

Following the recent release of the NVMe Express 2.0 specification, which includes support for traditional hard drives, Seagate unveiled its first mechanical hard drive design using an NVMe interface and PCIe channels at the Open Compute Project conference. This design allows for direct connection and operation without the need for any adapters or additional controller chips. For practical applications, this simplifies storage device port design, allowing for greater flexibility in design and installation. For example, desktop or server designs no longer require traditional SATA ports or additional controller chips, simplifying device design and enabling optimization for storage device configurations. However, given the current data transfer rates of traditional hard drives, they don't even fully utilize the bandwidth of PCIe 2.0 x1. But with the adoption of more controller chips and HAMR (Heat-Assisted Magnetic Recording) technology, overall access efficiency is expected to improve. Furthermore, the relatively low cost per unit of storage for traditional hard drives will bring greater benefits to future data storage needs. Seagate plans to provide samples of traditional hard drives with NVMe connectivity to large users in September 2022, but the official commercial product may not be launched until 2024.

The NVMe design, currently the standard for most SSDs, has recently been confirmed for version 2.0, with an expected 43% growth in usage by 2024. Its smaller interface makes it easier to install and use in thin and light laptops, allows for simpler desktop configurations, and even significantly reduces overall size. The use of PCIe ports further enhances data transfer speeds, making NVMe SSDs increasingly mainstream in recent years. The NVMe Technology Alliance's version 2.0 design incorporates Zoned Namespaces (ZNS), which allows data to be categorized and stored in specific SSD partitions based on usage frequency, improving data access efficiency and reducing the impact of repeated writes on SSD lifespan. Furthermore, the adoption of a new Endurance Group Management mechanism allows for more flexible SSD data access block planning, improving SSD storage control efficiency and enabling the system to effectively utilize SSD storage space. Other features include a design that integrates with traditional mechanical hard drives, meaning that traditional mechanical hard drives can achieve higher data transfer rates through the NVMe interface. The newly added Key Value instruction set will allow software services to utilize SSD resources more efficiently while reducing CPU resource usage. Samsung already presented an SSD prototype using this instruction set design in 2019, and Western Digital's recently launched Ultrastar DC ZN540 for data centers also uses this instruction set design.