Samsung earlier announced the launch ofProprietary 3D stacking packaging technology, and decided to name it X-Cube, expecting to reduce the size of its processors, which will make it easier for the processors to be used in smaller devices.
The name "X-Cube" derives from "eXtended-Cube," which shifts from a 2D planar package to a 3D stack. This allows the processor to pack more transistors into a limited area while also requiring less power. Samsung has previously used X-Cube packaging technology to stack SRAM layers on top of logic layers, interconnecting them via TSV (Through Silicon Vias), using its own 7nm EUV process technology.
Samsung said that the X-Cube packaging technology will reduce the signal transmission distance between the dies inside the processor, thereby speeding up data computing efficiency and reducing overall power loss. It also emphasized that this packaging technology can be applied to high-performance computing processors, 5G networking data chips, or artificial intelligence computing chips.
Currently, the X-Cube packaging technology has been verified in Samsung's 7nm and 5nm process technologies, and is ready to be applied to its own processor products or to assist other processor design manufacturers in producing products.
In addition to Samsung, current technologies include TSMC's CoWoS packaging technology and Intel's Foveros packaging technology. Both use the 3D stacking concept to accommodate more transistors inside the processor, thereby achieving higher computing performance.
