PCI-SIG announced earlierPCIe 7.0 Revision 0.5, and is open to all PCI-SIG members for use. It is expected that the official version 2025 specification will be successfully released in 1.0, allowing more companies to design PCIe 7.0 application products in accordance with the specification.
PCIe 7.0 0.5版主要延續去年6月公布的PCIe 7.0 0.3版修訂規範，包含對應128GT/s資料速率、以x16組態達成512GB/s雙向傳輸速率，以及支援PAM4傳輸訊號、改善電力使用效率，同時也能向下相容舊版PCIe規格。
This revised version allows PCIe to further correspond to the 800G Ethernet transmission specification and can be applied to supercomputing-scale computers, quantum computing, cloud collaborative computing, as well as design requirements such as artificial intelligence and machine learning that require higher data transmission rates.
Currently, PCIe transmission bandwidth is doubling almost every three years. For example, PCIe 5.0 can reach a raw bit transfer rate of 32 GT/s, and a bidirectional bit transfer rate of 16 GB/s through a x128 configuration. PCIe 6.0 can reach a bit transfer rate of 64 GT/s, and a bidirectional bit transfer rate of 16 GB/s through a x256 configuration. It is expected that the bit transfer rate will increase to 7.0 GT/s in PCIe 128, and a bidirectional bit transfer rate of 16 GB/s in a x512 configuration.
