Launched last yearThe first family of custom accelerator chips developed in-house, after the MTIA (Meta Training and Inference Accelerator) acceleration chip, which is specifically designed to handle inference-related tasks, MetaAnnounceroll outNew Customized Accelerator Chip, which will accelerate the underlying operations of content sorting and advertising recommendation, and is still manufactured by TSMC using a 5nm process.
The new generation of MTIA acceleration chips uses an 8 x 8 matrix computing architecture and an improved sparse computing pipeline design. In addition, with larger storage, memory, and transmission bandwidth, dense computing and sparse computing can be increased by 3.5 times and 7 times respectively. At the same time, by integrating the network function on the chip (NoC) design, the chip can adjust different computing methods under network latency conditions to cope with more complex workload patterns.
At the same time, the new generation MTIA acceleration chip operates at 1.35GHz, uses 128MB of memory, and a PCI Gen 5 transmission interface design, but its thermal design power consumption has increased to 90W, which is significantly more power-consuming than the previous generation chip with a 25W design.
As for software, it corresponds to PyTorch 2.0, layer capture, analysis, conversion, and acquisition mechanisms, making it directly compatible with the first-generation MTIA acceleration chip platform environment and related program coding.
Meta expects to replace the new chips with its existing computing environment in the near future. It is currently using the new chips to execute AI-related workloads in its 16 cloud regional data centers, while reducing its reliance on external acceleration chips such as NVIDIA.
