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Marvell unveiled its first 102.4 Tbps AI switch, the Teralynx T100, with NVIDIA showing strong support and calling it "the next trillion-dollar company."

The final mile after computing power and memory!

Author: Mash Yang
2026-06-03
in exhibition, Life, network, Processor
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On the opening day of COMPUTEX 2026, Marvell CEO Matt Murphy delivered a speech, officially announcing that the battleground for AI infrastructure has shifted from "computing power" to "connectivity." NVIDIA CEO Jensen Huang made a surprise appearance, stating to the audience that Marvell will be the next "trillion-dollar company."

Marvell unveiled its first 102.4 Tbps AI switch, the Teralynx T100, with NVIDIA showing strong support and calling it "the next trillion-dollar company."

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During this speech, Marvell took the opportunity to announce the industry's first switch chip designed specifically for the AI ​​era—the Teralynx T100—aiming to break down the "power wall" of current AI data centers with its extreme energy efficiency and transmission capabilities.

The third hurdle in AI infrastructure: from computing power and HBM high-bandwidth memory to connectivity.

In his speech, Matt Murphy proposed the "bottleneck migration" framework, arguing that the challenges of AI infrastructure are being overcome one by one, and each breakthrough will give rise to new trillion-level leaps in technology.

• The first hurdle is "computing power":NVIDIA provided the perfect solution with its GPUs, becoming the world's first super giant with a market capitalization exceeding $5 trillion.

• The second challenge is "Memory":HBM high-bandwidth memory suppliers have kept up with the massive throughput demand, and in the process, three new trillion-dollar companies have emerged.

• The third challenge is "connectivity":When the amount of data transmitted between chips and between racks increases exponentially, network bandwidth and power consumption become the biggest culprits dragging down the efficiency of the entire AI cluster.

For this final hurdle, Marvell positions itself as the industry's "undisputed connectivity leader." Matt Murphy emphasizes its unique market positioning: "We are the Switzerland of this industry, and we work with everyone." Amazon, Microsoft, Meta, and Google's Axion Arm architecture CPU business are all among its customers.

Teralynx T100, designed specifically for AI: Breaking down the power barrier of a 120KW rack

To address the bottleneck of medium- to long-distance data transmission, Marvell officially unveiled the Teralynx T100 switch chip the day before the presentation. This is not merely an upgrade to traditional networking technology, but a core infrastructure designed from scratch, entirely tailored for AI workloads.

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• A single-chip behemoth with 102.4 Tbps of bandwidth:The T100 uses an advanced 3nm process and a monolithic architecture, completely eliminating the unnecessary legacy packaging burdens found in traditional enterprise and cloud data center switches.

• Suppressing the power consumption monster:Currently, the power consumption of top-of-the-line GPU racks is approaching 120KW, pushing traditional air cooling to its limits. Switches and network equipment typically consume 15% to 25% of the rack's power. The T100 successfully reduces typical operating power consumption to below 1000 watts, approximately 25% lower than competing products on the market, allowing data centers to deploy more AI accelerators without adding additional power infrastructure.

• Flat, high-cardinality network architecture:For scale-out requirements, the T100 supports up to 512 ports in Radix; for scale-up, it supports protocols including ESUN Ethernet and the latest UEC (Ultra-Ethernet Alliance) standard, significantly reducing network layers and latency.

• Multi-package support:To handle extreme bandwidth, the T100 supports BGA, Copper Packaging (CPC), and the future flagship – Co-Packaging Optics (CPO), enabling hyperscale cloud operators to deploy flexibly. The chip has already begun sampling to customers this quarter.

From Copper Wall to Photonics: Heterogeneous Integration of CPO Technology and NVLink Fusion

During his presentation, Matt Murphy showcased everything from high-speed SerDes technology for die-to-die interconnects to optical digital signal processors (DSPs) that break through the physical limits of the "copper wall" by connecting within racks (2.5 to 7 meters).

Even more noteworthy is the switch prototype equipped with co-packaged optics technology. Compared to traditional switches surrounded by bulky pluggable fiber optic modules, CPO integrates the optical components directly into the package, significantly reducing both size and power consumption.

All of this technological development is inseparable from the deep alliance with NVIDIA. In March of this year, NVIDIA invested $20 billion in Marvell and, through the opening of NVLink Fusion technology, enabled cloud service providers to seamlessly integrate Marvell's customized XPUs or ASICs directly into NVIDIA's computing backbone.

In addition, Marvell recently acquired Celestial AI for up to $55 billion, gaining key photonic fabric technology and further consolidating its technological advantage in the silicon photonics field.

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Tags: ComputexComputex 2026MarvellNvidia
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Mash Yang

Mash Yang

Founder and editor of mashdigi.com, and student of technology journalism.

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