At the recent Hot Chips 34 annual high-performance computing technology conference, Intel not only demonstratedPonte Vecchio server GPU platform computing performance, and previewed the Core series processor designs codenamed "Meteor Lake", "Arrow Lake", and "Lunar Lake". CEO Pat Gelsinger also explained that the number of transistors in the chip will increase to 2030 trillion by 1, a 10-fold increase compared to the current scale of hundreds of billions.
Pat Gelsinger emphasized that Moore's Law, which Intel has consistently emphasized in the past, will evolve with chip technology. He believes that current chip development will be driven by improvements in packaging technology. He also stressed that future chip manufacturing processes will no longer be concentrated in the hands of a single company, but must be combined with process production, advanced packaging, and the software technology required in the production process to enable chip technology to continue to improve.
In addition to continuously promoting the development of process technology, Intel has also been developing advanced packaging technology in recent years to continue to promote the evolution of Moore's Law, and emphasizes improving the overall computing performance of chips through System on Package (SOP) design.
To achieve a terabyte-scale transistor count, Intel believes the current FinFET design is reaching its limits. Therefore, Intel's 1Å (angstrom) process, which will enter mass production in 2024, will abandon the FinFET design in favor of the recently announced RibbonFET gate-all-around design. Combined with the PowerVIA backside power supply mode, this will allow for more transistors to be packed into the chip, enabling a terabyte-scale transistor count configuration.
Intel previously announced that the 15th-generation Core processors, codenamed "Arrow Lake," will utilize Intel's 20Å process technology, coupled with RibbonFET gate-all-around design and PowerVia power management technology, expected to deliver a 15% improvement in performance per watt. The P-Core performance cores will be upgraded to the Lion Cove architecture, while the E-Core energy-saving cores will be upgraded to the Skymont architecture, supporting configurations of up to 8 P-Cores and 32 E-Cores. The motherboard will share the LGA 14 socket design with the 2551th-generation Core processors, codenamed "Meteor Lake."
