Intel Foundry announced new breakthroughs at the 2024 IEEE International Electron Components Meeting (IEDM), which will help propel the semiconductor industry into the next decade and beyond.
Intel Foundry demonstrated new materials that help improve intra-chip interconnects, increasing transistor capacity by 25% through the use of subtractive ruthenium. Furthermore, Intel Foundry used advanced packaging for heterogeneous integration solutions, achieving a 100-fold increase in throughput for the first time, enabling ultra-fast chip-to-chip assembly.
To further advance Gate-All-Around (GAA) scaling, Intel Foundry also demonstrated work on silicon RibbonFET CMOS and gate oxide modules for scaling 2D FETs, which can improve device performance.
Sanjay Natarajan, senior vice president of Intel Foundry and general manager of Device Research, said, "Intel Foundry continues to define and shape the semiconductor industry's future. This latest breakthrough demonstrates Intel's commitment to developing leading-edge technology. With support from the US CHIPS Act, Intel will continue to help improve the balance of the global supply chain."
To improve performance and interconnects within the chip, Intel Foundry demonstrated subtractive ruthenium as a key alternative metallization material, using thin-film resistors and air gaps to achieve significant progress in interconnect scaling. The team was the first to demonstrate a practical, cost-effective, and mass-production-suitable subtractive ruthenium integration process in an R&D test tool. This process, featuring air gaps, eliminates the need for photolithographic air gap exclusion zones around the vias and selectively etched self-aligned vias.
The use of subtractive ruthenium with airgap properties can reduce line capacitance by up to 25% at pitches ≤25 nanometers (nm), highlighting the advantages of subtractive ruthenium metallization as a replacement for copper damascene in tight pitches. This solution will be available in future nodes of Intel's foundry.
To enable ultra-high-speed chip-to-chip assembly in advanced packaging and increase throughput by 100 times, Intel Foundry demonstrated Selective Layer Migration Technology (SLT) for the first time. This heterogeneous integration solution allows for greater flexibility in ultra-thin chiplets. Compared to traditional chip-to-wafer bonding, the die size can be smaller and the aspect ratio higher, further enabling higher functional density. It also provides a more flexible and cost-effective solution for the mixing of specific chiplets from one wafer to another, or for fusion bonding, thereby improving the efficiency and flexibility of AI application architectures.
To push the limits of silicon scaling for wraparound gate-ribbonFETs, Intel Foundry has demonstrated a silicon RibbonFET CMOS (complementary metal-oxide-semiconductor) transistor with a gate length of 6nm. This device maintains industry-leading short-channel effects and performance despite significantly reduced gate length and channel thickness. Shortening gate length is a key cornerstone of Moore's Law, and this technological advancement opens a new chapter in gate length scaling.
Intel Foundry also showcased its achievements in GAA 2D NMOS and PMOS transistor manufacturing, with gate lengths down to 30 nanometers, and a particular focus on gate oxide (Gox) module development. This research highlights the industry's research into two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors, which may replace silicon in advanced transistor manufacturing processes in the future.
Additionally, Intel Foundry continues to advance the industry's first 300mm gallium nitride (GaN) technology, an emerging technology for power supply and radio frequency (RF) electronics. Compared to silicon, GaN offers higher efficiency and can withstand higher voltages and temperatures. This is the industry's first high-performance, scaled enhancement-mode GaN metal oxide semiconductor high electron mobility transistor (GaN MOSHEMT) fabricated on a 300mm GaN-on-TRSOI (trap-rich silicon-on-insulator) substrate.
GaN-on-TRSOI's advanced substrate design can achieve better signal linearity by reducing signal loss, and enable advanced integration solutions through backside substrate processing, achieving higher performance in RF and power electronics applications.
