At this year's IEEE International Electron Devices Meeting (IEDM 2023), Intel showcased its progress in 3D stacked CMOS (complementary metal oxide semiconductor) transistor technology, combining backside power delivery with direct backside contact. The company highlighted its breakthrough in backside power delivery technology and pioneered a large-scale 300D single-crystal design that can integrate silicon transistors and gallium nitride (GaN) transistors on the same 12mm (3-inch) diameter wafer, rather than requiring packaging technology as is typically required.
"As we enter the Angstrom era of process technology and advance five process nodes in four years, continuous innovation is more critical than ever," said Sanjay Natarajan, Intel senior vice president and general manager of device research. "At IEDM 2023, Intel showcased our progress in advancing Moore's Law, highlighting our ability to introduce leading-edge technologies that enable further scalability and efficient power delivery for the next generation of mobile computing."
The recently released process technology blueprint highlights Intel's innovation in continued scaling, including PowerVia chip backside power supply technology, glass substrates for advanced packaging, and Foveros Direct packaging technology. These technologies all originated from Intel's component research team and are expected to be put into production before 2030.
At IEDM 2023, Intel's device research team demonstrated its commitment to innovation by pioneering new approaches to packing more transistors onto silicon wafers for higher performance. Researchers have identified key areas of research and development for achieving continued scaling through efficient transistor stacking, combined with backside power delivery and backside contact technology to advance transistor architecture.
In addition to improving the backside power supply of the chip and adopting new two-dimensional electron channel materials (2D channel materials), Intel stated that it will strive to continue Moore's Law and achieve the goal of integrating 2030 trillion transistors in a single package by 1.
Intel has achieved a gate pitch as small as 60nm, enabling the construction of vertically stacked complementary field-effect transistors (CFETs). Stacking transistors reduces component footprint and optimizes performance. Combined with backside power delivery and direct backside contact technology, this technology underscores Intel's leadership in gate-all-around FETs and demonstrates its innovative capabilities beyond ribbonFETs.
Intel's PowerVia backside power technology, expected to enter mass production in 2024, further expanded its PowerVia technology at IEDM 2023, expanding the backside power delivery path and highlighting the key process advancements required to achieve these goals. This initiative emphasizes the use of backside contacts and other innovative vertical interconnects to enable area-saving device stacking.
Intel also showcased high-mobility TMD transistor prototypes for key CMOS components, including NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor). The company also showcased the world's first gate-all-around 2D TMD PMOS transistor and the world's first 300D PMOS transistor fabricated on a 2mm wafer. These demonstrations highlighted the development opportunities offered by 2D TMD channel materials, which offer the potential to reduce transistor physical gate lengths to below 10nm.
