With the explosive growth of artificial intelligence (AI) and machine learning (ML) applications, data center transmission efficiency has long been a bottleneck that manufacturers are eager to overcome. Richard Solomon, Vice President of PCI-SIG, the organization that defines the PCI Express (PCIe) industry standard, announced the latest technology roadmap for 2026 at the developer conference in Taipei today (February 9th), unveiling the mystery of PCIe 8.0 and emphasizing that "optical interconnects" will be a key piece of the puzzle for future high-performance computing.
PCIe 8.0 draft emerges: a promise to double bandwidth every three years.
Richard Solomon reiterated at the meeting that PCI-SIG has consistently maintained a technology evolution pace of "doubling bandwidth every three years." This will be followed by the announcement in mid-June 2025.PCIe 7.0 official specificationsSubsequently, the draft version 0.3 of the next-generation PCIe 8.0 specification was released in September 2025.
According to the current plan, the main highlights of PCIe 8.0 include:
• Double the transmission rate:The raw bit rate will be increased from 128.0 GT/s in PCIe 7.0 to 256.0 GT/s.
• Amazing bandwidth:In the x16 configuration, the bidirectional bandwidth is expected to reach the milestone of 1 TB/s.
• Technological continuity:It will continue to use PAM4 signal transmission and Flit encoding technology, and will ensure backward compatibility with previous generation technologies.
PCI-SIG expects to officially release the full PCIe 8.0 specification to its members in 2028.
Introduction of Optical Technology: Solving the "Shore-line" Challenge of AI Platforms
In the fields of AI and high-performance computing (HPC), traditional copper cabling solutions are facing severe challenges in terms of transmission distance and signal loss. To address this, the PCI-SIG issued the industry's first standardized Optical Aware Retimer Engineering Change Notice (ECN) in June 2025.
The core value of this technology lies in:
• Seamless transition:It can be easily ported to existing PCIe 6.0 and 7.0 designs, and is already planned for inclusion in future PCIe 8.0.
• Expansion capabilities:This enables PCIe architecture to interconnect Pods over long distances across racks.
• Size advantage:Compared to bulky electronic copper cables, optical solutions enable more streamlined, high-density hardware deployments.
CopprLink Internal and External Cable Application Scenarios Analysis
CopprLink is a cable specification specifically developed by PCI-SIG to meet the demands for transmission distance and topology flexibility in the era of AI and big data. Its application scenarios are divided into two types: internal and external.
Internal cable
• SNIA SFF-TA-1016 connector is used:The maximum distance is about 1 meter, and it is mainly used for dense connections within a single system.
• Chip-to-Chip:It directly connects to multiple computing chips on the motherboard, improving data exchange efficiency.
• Motherboard to AIC:Connects the CPU to various high-performance accelerator cards (such as GPUs).
• Motherboard to Backplane:Directing PCIe signals to the storage backplane is common in high-performance server nodes.
• Storage nodes:It is used for connecting NVMe SSD storage arrays within data center computing nodes.
External Cable
• SNIA SFF-TA-1032 connector is used:With a maximum distance of up to 2 meters, it locks in the interconnection between distributed architectures and racks.
• Rack-to-Rack:It connects computing units between different racks, making it suitable for ultra-large-scale data centers.
• Accelerator Fabrics:In AI/ML computing clusters, this is used to connect the CPU to a remote GPU or dedicated accelerator pool.
• Decoupled Servers:This enables physical separation between the CPU and storage devices (CPU-to-Storage) or memory expansion (CPU-to-Memory), increasing the flexibility of hardware configuration.
• Shared resource pool:Suitable for shared storage pools or RAM expansion, allowing the system to achieve physical partitioning while maintaining bandwidth.
Taiwan's key role in industry: the world's second largest developer community
Richard Solomon specifically pointed out that Taiwan plays a pivotal role in the PCIe ecosystem. Currently, the PCI-SIG has over 1000 member companies worldwide, with 103 of them headquartered in Taiwan, including technology companies such as Acer, ASUS, MediaTek, Realtek, and Wistron.
Furthermore, the developer conference to be held in Taipei in 2026 attracted more than 500 professionals, ranking among the top in the world. This not only demonstrates the demand of Taiwanese hardware developers for high bandwidth specifications, but also reflects Taiwan's core influence in the global data center and server supply chain.
The expected release schedule for the PCIe 7.0 integrator list.
According to Richard Solomon, it typically takes about three years for a specification to go from official release to inclusion in the "Integrator List".
• Official specifications released:The PCIe 7.0 version 1.0 specification was officially released in June 2025.
• Preliminary compatibility testing (Pre-FYI Testing):This process typically takes place two years after the specification is released, and is expected to begin in 2027.
• The list has been officially announced:Based on a three-year development and testing cycle, the list of PCIe 7.0 integrators is expected to be announced in 2028.
• Product launch date:Although the list is scheduled for 2028, early chips and hardware products supporting PCIe 7.0 (such as motherboards and GPUs) are expected to appear on the market as early as 2026 to 2027.
Analysis of viewpoints
From PCIe 7.0 to 8.0, what we are seeing is not simply a competition of specifications and numbers, but an infrastructure revolution to cope with the explosion of AI computing power. In particular, the integration of the CopprLink cable specification and optical technology means that PCIe will evolve from a simple "onboard bus" to a "system interconnect fabric" that spans racks.
For Taiwanese manufacturers, maintaining signal integrity in next-generation specifications and gaining an early advantage in the new field of optical interconnects will be the main focus of technological competition in the next three to five years.
