Fueled by the exponential growth in bandwidth demands from AI computing and data centers, the evolution of underlying transmission interfaces is accelerating at an alarming pace. Al Yanes, President and Chairman of the PCI-SIG, which developed the PCI Express specification, announced...PCIe 8.0 specificationDraft version 0.5 has been officially provided to members for review. This official first draft is not only ahead of schedule, but also establishes the goal of achieving up to 1.0 TB/s bidirectional transmission bandwidth in an x16 channel configuration.
Based on the current pace of development, PCIe 8.0 is expected to be officially released in 2028.
Ahead of schedule: Based on feedback from version 0.3, the 2028 target remains unchanged.
In September 2025, the PCI-SIG released the 0.3 draft of PCIe 8.0, and after extensively collecting feedback from member companies, successfully and quickly launched the 0.5 version announced this time. Al Yanes emphasized that compared to the past specification development timeline, the release of this 0.5 draft is "significantly ahead of schedule," demonstrating the industry's urgent desire for next-generation high-frequency broadband interfaces, and also ensuring that PCIe 8.0 can usher in the final official version as scheduled in 2028.
PCIe 8.0 Core Upgrade: Not Just Doubling Speed, But Also Evaluating a "New Connector"
As a next-generation standard, PCIe 8.0 maintains the alliance's glorious tradition of "doubling bandwidth with each generation." According to information released by PCI-SIG, the core goals and key upgrades of PCIe 8.0 include:
• Sky-high transmission rates:It offers a raw bit rate of up to 256.0 GT/s. In the most mainstream x16 channel configuration, it can achieve a bidirectional total bandwidth of up to 1.0 TB/s.
• Evaluating new connector technologies:To address such extreme challenges of ultra-high frequency and signal integrity, PCI-SIG has stated that it is evaluating new connector technologies.
• Strict latency and reliability requirements:To ensure that the established goals of low latency, forward error correction (FEC), and data transmission reliability can still be achieved under extremely high bandwidth.
• Maintaining downward compatibility: Like previous generations of PCIe specifications, PCIe 8.0 must maintain backward compatibility with all previous generations of PCIe technology.
• Underlying architecture optimization:The available bandwidth is further increased through enhancements to the protocol layer, and additional technologies are introduced to reduce overall power consumption.
Targeting the bottomless demand for AI, data centers, and quantum computing.
Why do we need such fast transmission speeds? The PCI-SIG points out several key data-intensive markets, including AI, large data centers, high-speed network infrastructure, edge computing, and even the promising future of quantum computing. Without exception, these areas require extremely high bandwidth and extremely low latency to overcome the bottlenecks in data transmission between computing nodes.
Currently, PCI-SIG members can access this latest draft version 0.5 through the Causeway platform and participate in subsequent specification development work.
Analysis of viewpoints
The "overtaking" of the PCIe 8.0 draft progress reflects the anxiety of the current AI hardware arms race.
With the soaring computing power of AI accelerators developed by NVIDIA, AMD, and major cloud giants (AWS, Google Cloud, Microsoft, etc.), the data throughput between GPUs and CPUs, or between accelerators and high-speed network cards (such as 800G/1.6T Ethernet), has long been straining the existing PCIe interface. Although NVIDIA has already proposed NVLink, a proprietary interconnect technology that can handle higher bandwidth, the server's underlying external I/O and cross-architecture ecosystem still heavily rely on the PCIe connectivity standard.
The most intriguing detail in this PCIe 8.0 specification is the description of "evaluating new connector technologies".
Over the past two decades, the appearance of the PCIe slots we are familiar with has hardly changed. However, to achieve 256.0 GT/s signal transmission over copper wires, the physical challenges of signal loss and integrity will reach unprecedented levels.
This means that in the PCIe 8.0 era, traditional CEM (Extension Card Electrical Mechanism Specification) slots may face significant changes. We may see more cable routing-based connection solutions, and even accelerate the practical application of optical interconnects (CPO) on the PCIe interface. This is not just an upgrade in speed, but also a major reshuffling of the internal physical structure of servers.
