AMD has announced that its Spartan UltraScale+ FPGA series has officially entered mass production, with the first wave of three small devices: the SU10P, SU25P, and SU35P. These devices are now available for order and fully support the latest Vivado 2025.1 design suite, marking the official launch of the series' layout for the edge application market.
The Spartan UltraScale+ series focuses on the strategic positioning of "cost optimization + high-performance applications." Building on the stability and reliability of the AMD UltraScale+ architecture, it enhances low power consumption, high I/O count, and security protection, providing cost-effective solutions specifically for areas such as machine vision, industrial control, medical equipment, board-level I/O expansion, and edge AI processing.
Multiple core upgrades meet edge design requirements
Compared to the previous Spartan series, the new UltraScale+ architecture emphasizes "high I/O density to logic resource ratio." It adds XP3.3IO high-speed signal support based on 5V HDIO, enabling high-speed differential signal transmission such as LVDS and MIPI D-PHY, with interface speeds reaching 3.2 Gb/s.
At the same time, Spartan UltraScale+ also incorporates the same LPDDR4X/5 memory controller as the flagship FPGA, supporting a maximum transfer rate of 4266 Mb/s. This can effectively reduce design resource usage, reduce the number of logic units, and further lower power consumption and total cost.
Meeting the needs of security and rapid deployment
To address the growing threat of IoT and edge attacks, the Spartan UltraScale+ processor features a built-in hardware-level security engine that supports NIST-certified post-quantum cryptographic algorithms. Combined with a hardware-level True Random Number Generator (TRNG), PUF, and secure hashing, it can adapt to future security architecture upgrades.
In addition, with the latest version of the Vivado design tool, developers can achieve one-click timing closure, rapid debugging, and cross-project IP reuse, accelerating the design process and reducing the risk of introducing new projects.
PCIe Gen4 and 8 SPI channels for enhanced data transfer
In terms of connectivity, the Spartan UltraScale+ has a built-in PCIe Gen4 hard IP module that supports terminal and root port applications, and a built-in 8-channel SPI controller to meet high-speed flash memory read and write requirements, improving configuration efficiency and data throughput.
Summary: FPGA's new weapon for entering the entry-level edge market
With the first wave of Spartan UltraScale+ devices, including SU10P to SU35P, entering mass production, AMD has successfully extended its flagship technology to cost-sensitive markets, providing developers with highly flexible and reliable FPGA solutions without sacrificing security or performance.
Next, as more density levels are launched, Spartan UltraScale+ is expected to further consolidate AMD's presence in the low- and mid-range edge computing markets, forming a more complete product portfolio with the existing Zynq SoC series.
